VHDL Notes

Type Conversion

use ieee.numeric_std.all;

+------------+   to_signed(I, S'length)   +------------+
|            | -------------------------> |            |
| integer I  |                            | signed S   |
|            | <------------------------- |            |
+------------+      to_integer(S)         +------------+
  |      ^                                   |      ^
  |      |                                   |      |
  |-to_unsigned(I, U'length)                 |-std_logic_vector(S)
  |      |                                   |      |
  |      |                                   |      |
  |      |-to_ingeger(U)                     |      |-signed(V)
  |      |                                   |      |
  v      |                                   v      |
+------------+   std_logic_vector(U)      +--------------------+
|            | -------------------------> |                    |
| unsigned U |                            | std_logic_vector V |
|            | <------------------------- |                    |
+------------+      unsigned(V)           +--------------------+

Shifting

VHDL uses functions for arithmetic and logical shifts. They are part of ieee.numeric_std and ieee.numeric_bit. These packages provide the following functions:

The functions are overloaded for different types. So the type of the first argument determines whether it's an arithmetic or logical shift. For example for an arithmetic right shift of a std_logic_vector, the signal has to be converted to a signed and then passed to shift_right(). For a logical shift, the signals should be converted to an unsigned and passed to shift_right().